The function of an integrated circuit package is to provide protection of the circuit, distribute power and signals, and dissipate heat. Rapid advances in semiconductor technology have out paced developments in semiconductor packaging techniques. Specifically, increases in the number of signal and power connections on integrated circuits, larger chip sizes, increased power consumption and higher operating frequencies strain the ability of traditional semiconductor packages to provide reliable, cost-effective performance. While some recent advances in packaging technologies have begun to address some of the needs of higher performance integrated circuits, improved packaging technologies are still needed to allow high I/O count and increased density integrated circuits to perform to levels intended by their designers.
Packaging technologies, such as thin quad flat packs (TQFPs), ball grid arrays (BGAs), tape automated bonding (TAB), ultra-thin packages, bare chips or chip-on-board (COB), flip-chip assemblies and multichip modules (MCMs) are now being developed and improved to address performance issues.
In a BGA, in lieu of package pins, an array of solder balls is located on the bottom of a substrate permitting higher I/O counts. BGA yields are almost the same as those for fine-pitch packages. Further, BGA packages will withstand some degree of mishandling without damaging the leads, whereas fine lead parts must be handled with care before soldering so that the leads are not bent or broken. However, BGA packaging has its own downsides such as:                BGAs are more costly to test        BGAs are harder to rework        BGAs require HDI (High Density Interconnect) PCBs which are more expensive.Currently BGA packaging is the most common technique being used for stacking BGA devices or designing MCMs (Multi Chip Modules).        
FIG. 1 illustrates conventional BGA semiconductor packages 102, 104, and 106 coupled to a main board 108. Only one side of each PCB 110, 112, and 114 can be populated while the other side will be used for BGA interconnect balls 116, 118, and 120. Thus, in order to package multiple chips 102 and 104 on the PCB 114, horizontal planar space is needed on the PCB 114. PCB 114 comprises a dielectric substrate (not shown). Conductive traces (not shown) are formed on each side of the substrate to form predetermined circuit patterns on each side of the dielectric substrate. Solder balls 120 are electrically connected to the conductive traces on the bottom surface of the PCB 114.
With BGA packaging, the substrate is limited to the surface on only one side of the PCB since the other side is used for BGA interconnect balls. Thus, no more than one die can be allowed on any single lead frame.
Accordingly, a need exists for a single IC packaging solution for multi chip modules. A primary purpose of the present invention is to solve these needs and provide further, related advantages.